Cypress Semiconductor /psoc63 /FLASHC /CM0_CA_CTL2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CM0_CA_CTL2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PWRUP_DELAY

Description

CM0+ cache control

Fields

PWRUP_DELAY

Number clock cycles delay needed after power domain power up

Links

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